안녕하세요.

회로도를 변경해서 ECO를 적용하면 변경된 부품들이 (0, 0)에 생성은 되긴 하나 일부 NET의 이름이 예전 회로도대로 남아 있습니다.

.eco 파일 import 시 아래와 같은 내용의 메모장이 뜨는데 어떤 부분이 잘못 되어서 그런걸까요?

** ECO In Report **

Thu Aug 01 13:34:20 2024

Input  File : \\10.1.1.100\file_server\200. 부서\광영상연구소\개발프로젝트관리\VTS-16K5X2\회로도 검토\VT-CXP12_4CH-FPGA_Artwork_2318-3301-01A(220927)-GBR.eco

Current Job : VT-CXP12_4CH-FPGA_Artwork_2318-3301-01A(220927)-GBR.pcb

Line 140 , Section *SPLITNET*

*SIGNAL*  VCC_3V3

* Net name VCC_3V3 already used

Line 146 , Section *SPLITNET*

* WARNING: Splitting a Net VCC_3V3 in desired fashion requires deletion of more than one connection

* Deleting connection FCON6.13-FCON2.2 ...

* Deleting connection FCON6.15-FCON2.2 ...

* Deleting connection FCON6.17-FCON2.2 ...

* Deleting connection FCON6.19-FCON2.2 ...

* Deleting connection FCON2.2-FC436.2 ...

* WARNING: Added connection between FCON6.13 FCON6.15 to keep continuity of net VCC_4V0

* WARNING: Added connection between FCON6.15 FCON6.17 to keep continuity of net VCC_4V0

* WARNING: Added connection between FCON6.17 FCON6.19 to keep continuity of net VCC_4V0

* WARNING: Added connection between FCON6.19 FC436.2 to keep continuity of net VCC_4V0